Dr. W. R. Bottoms, Chairman, Third Millennium Test Solutions, gave a great presentation at the event. Some of the highlights, for me, included:
- For some products, packaging and test make up more than 2/3 of the final cost. The actual die in the package might account for less than 30% of the final cost.
- Consumer electronics is driving the semiconductor market, and consumers are demanding devices that do a better job of interacting with people.
- The near term driving forces for Vertical Integration include:
- Miniaturization — (reduced volume and weight)
- Increased performance
- Reduced power consumption
- Mixed functional integration
- Longer term, reduced cost will also be an important driving force.
- Everything (Architectures, Materials, Processes, …) is changing.
- Dr. Bottoms asserts that the semiconductor industry's future growth depends on vertical integration.
- The concept of "Known Good Die" will be replaced by "Probably Good Die."
- Transistors are fast enough, and efficient enough. Interconnect dominates speed & power constraints. Vertical integration is the most straightforward way to minimize interconnect. For "n" stacked layers, interconnect decreases by the square root on "n" (sorry, I couldn't figure out how to represent the symbol in blogger).
- Elpida has a 3-D DDR3 memory module, based on TSV, with 9 layers (8 memory die and 1 memory controller). The current generation product has an 8Gbit capacity, with a 16Gbit product coming in April (Unfortunately, I couldn’t find the part on their products page). Samsung is also coming along with a similar product.
- We have found, or soon will find, solutions to address each of the Four Horsemen
- We will see high volume commercial shipments of 3-D products in 2010
Some other interesting bits that I picked up include: Micron is developing 3-D fab technology for in-house use, and they are hiring for the effort in Boise. IMEC is also hiring, if Belgium is your glass of Stella Artois.
In response to a question from the audience, Dr. Bottoms acknowledged that current design tools are not up to the challenge of 3-D. They solve some parts of the problem, but none of the vendors have yet fielded a complete solution (although, all of the design tool vendors that I've talked with claim that their current suites fully address 3-D design). There is a real opportunity out there for my friends at Cadence, Mentor and Synopsys.
Pretty much everything that we heard at the meeting is in line with what we're seeing as we move forward with 4D Chips, so I really appreciated the discussion. The slides from the event (PDF 1.6 MB) are posted up on the IEEE CPMT-SCV site. They're definitely worth a look.